Repository logo
 

Sensitivity analysis of critical parameters in board test

Simple item page
dc.contributor.authorTegethoff, Mick M. V., author
dc.contributor.authorChen, Tom W., author
dc.contributor.authorIEEE, publisher
dc.date.accessioned2007-01-03T06:15:58Z
dc.date.available2007-01-03T06:15:58Z
dc.date.issued1996
dc.description.abstractThe authors analyze the main contributors to the quality and cost of complex boards. With manufacturing data from Hewlett-Packard boards, they use simulation models to derive the sensitivity of quality and cost to the solder defect rate, the functional defect rate, and test coverage. They also give a simple cost estimate of implementing IEEE 1149.1 boundary scan on ASICs. Their new yield model, which accounts for solder defect clustering, provides highly accurate yield predictions.
dc.format.mediumborn digital
dc.format.mediumarticles
dc.identifier.bibliographicCitationTegethoff, Mick M. V. and Tom W. Chen, Sensitivity Analysis of Critical Parameters in Board Test, IEEE Design & Test of Computers 13, no. 1 (Spring 1996): 58-63.
dc.identifier.urihttp://hdl.handle.net/10217/1204
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartofFaculty Publications
dc.rights©1996 IEEE.
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjectsensitivity analysis
dc.subjectprinted circuits
dc.subjectCAD
dc.subjectprinted circuit testing
dc.titleSensitivity analysis of critical parameters in board test
dc.typeText

Files

Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
ECEtwc00001.pdf
Size:
682 KB
Format:
Adobe Portable Document Format
Description:
Download

Collections

Faculty Publications