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Heterogeneous prioritization for network-on-chip based multi-core systems

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dc.contributor.authorPimpalkhute, Tejasi, author
dc.contributor.authorPasricha, Sudeep, advisor
dc.contributor.authorBohm, Wim, committee member
dc.contributor.authorJayasumana, Anura, committee member
dc.date.accessioned2007-01-03T06:11:33Z
dc.date.available2015-01-31T05:57:00Z
dc.date.issued2013
dc.description.abstractIn chip multi-processor (CMP) systems, communication and memory access both play an important role in influencing the performance achievable by the system. The manner in which the network packets (on-chip cache requests/responses) and off-chip memory bound packets are handled, in multi-core environment with several applications executing in parallel, determines end-to-end latencies across the network and memory. Several techniques have been proposed in the past that schedule packets in either an application-aware manner or memory requests in a DRAM row/bank locality-aware manner. Prioritization of memory requests is a major factor in increasing the overall system throughput. Moreover, with the increasing diversity in CMP systems, applying the same prioritization rules to all packets traversing the NoC as is done in the current implementations may no longer be a viable approach. In this thesis, a holistic framework is proposed that integrates novel prioritization techniques for both network and memory accesses and operates cohesively in an application-aware and memory-aware manner to optimize overall system performance. The application-aware technique makes fine grain classification of applications with a newly proposed ranking scheme. Two novel memory-prioritization algorithms are also proposed, one of which is specifically tuned for high-speed memories. Upon analyzing the fairness issues that arise in a multi-core environment, a novel strategy is proposed and employed system-wide to ensure fairness in the system. The proposed heterogeneous prioritization framework is validated using a detailed cycle-accurate full system event-driven simulator and shows significant improvement over Round Robin and other recently proposed network and memory prioritization techniques.
dc.format.mediumborn digital
dc.format.mediummasters theses
dc.identifierPimpalkhute_colostate_0053N_12147.pdf
dc.identifierETDF2013500410ECEN
dc.identifier.urihttp://hdl.handle.net/10217/81054
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartof2000-2019
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjectmulti-core systems
dc.subjectoff-chip memory
dc.subjectnetwork-on-chip
dc.titleHeterogeneous prioritization for network-on-chip based multi-core systems
dc.typeText
dcterms.embargo.expires2015-01-31
dcterms.embargo.terms2015-01-31
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorColorado State University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science (M.S.)

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