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A parallel algorithm and architecture for the control of kinematically redundant manipulators

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dc.contributor.authorReagin, James M., author
dc.contributor.authorMaciejewski, Anthony A., author
dc.contributor.authorIEEE, publisher
dc.date.accessioned2007-01-03T06:16:23Z
dc.date.available2007-01-03T06:16:23Z
dc.date.issued1992
dc.description.abstractThis work presents a parallel algorithm for solving the equations of motion for kinematically redundant robotic systems. This algorithm, which relies on the calculation of the Singular Value Decomposition (SVD), is implemented on a simple linear array of processing elements. By taking advantage of the error bounds on the perturbation of the SVD, it is shown that an array of only four AT&T DSP chips can result in control cycle times of less than 3 milliseconds for a seven degree-of-freedom manipulator.
dc.description.sponsorshipThis work was supported in part by the NEC Corporation, the TRW Foundation, and General Motors.
dc.format.mediumborn digital
dc.format.mediumproceedings (reports)
dc.identifier.bibliographicCitationMaciejewski, Anthony A. and James M. Reagin, A Parallel Algorithm and Architecture for the Control of Kinematically Redundant Manipulators, Proceedings: 1992 IEEE International Conference on Robotics and Automation, May 12-14, 1992, Nice, France: 488-493.
dc.identifier.urihttp://hdl.handle.net/10217/1209
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartofFaculty Publications
dc.rights©1992 IEEE.
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjectparallel algorithms
dc.subjectmanipulators
dc.subjectkinematics
dc.subjectdigital signal processing chips
dc.subjectparallel architectures
dc.subjectredundancy
dc.titleA parallel algorithm and architecture for the control of kinematically redundant manipulators
dc.typeText

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