Optimal design space exploration for FPGA-based accelerators: a case study on 1-D FDTD
| dc.contributor.author | Puranik, Mugdha, author | |
| dc.contributor.author | Rajopadhye, Sanjay, advisor | |
| dc.contributor.author | Pasricha, Sudeep, committee member | |
| dc.contributor.author | Malaiya, Yashwant, committee member | |
| dc.date.accessioned | 2016-01-11T15:13:44Z | |
| dc.date.available | 2016-01-11T15:13:44Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Hardware accelerators are optimized functional blocks designed to offload specific tasks from the CPU, speed up them up and reduce their dynamic power consumption. It is important to develop a methodology to efficiently implement critical algorithms on the hardware accelerator and do systematic design space exploration to identify optimal designs. In this thesis, we design, as a case study, a hardware accelerator for the 1-D Finite Difference Time Domain (FDTD) algorithm, a compute intensive technique for modeling electromagnetic behavior. Memory limitations and bandwidth constraints result in long run times on large problems. Hence, an approach which increases the speed of the FDTD method and reduces bandwidth requirement is necessary. To achieve this, we design an FPGA based hardware accelerator. We implement the accelerator based on time-space tiling. In our design, p processing elements (PEs) execute p parallelogram shaped tiles in parallel, each of which constitutes one tile pass. Our design uses a small amount of redundant computation to enable all PEs to start "nearly" concurrently, thereby fully exploiting the available parallelism. A further optimization allows us to reduce the main memory data transfers of this design by a factor of two. These optimizations are integrated in hardware, and implemented in Verilog in Altera's Quartus II, yielding a PE that delivers a throughput of one "iteration (i.e., two results) per cycle". To explore the feasible design space systematically, we formulate an optimization problem with the objective of minimizing the total execution time for given resource constraints. We solve the optimization problem analytically, and therefore have a provably optimal design in the feasible space. We also observe that for different problem sizes reveal that the optimal design may not always match the common sense intuition. | |
| dc.format.medium | born digital | |
| dc.format.medium | masters theses | |
| dc.identifier | Puranik_colostate_0053N_13299.pdf | |
| dc.identifier.uri | http://hdl.handle.net/10217/170328 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | hardware accelerators | |
| dc.subject | stencil computations | |
| dc.title | Optimal design space exploration for FPGA-based accelerators: a case study on 1-D FDTD | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science (M.S.) |
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