Parameterized and multi-level tiled loop generation
| dc.contributor.author | Kim, DaeGon, author | |
| dc.contributor.author | Rajopadhye, Sanjay Vishnu, advisor | |
| dc.contributor.author | Böhm, Anton Pedro Willem, 1948-, committee member | |
| dc.contributor.author | Chong, Edwin Kah Pin, committee member | |
| dc.contributor.author | Strout, Michelle Mills, 1974-, committee member | |
| dc.date.accessioned | 2007-01-03T05:45:09Z | |
| dc.date.available | 2007-01-03T05:45:09Z | |
| dc.date.issued | 2010 | |
| dc.description | Department Head: L. Darrell Whitley. | |
| dc.description.abstract | Tiling is a loop transformation that decomposes computations into a set of smaller computation blocks. The transformation has been proven to be useful for many high-level program optimizations, such as data locality optimization and exploiting coarse-grained parallelism, and crucial for architecture with limited resources, such as embedded systems, GPUs, and the Cell architecture. Data locality and parallelism will continue to serve as major vehicles for achieving high performance on modern architecture in multi-core era. In parameterized tiling the size of blocks is not fixed at compile time but remains a symbolic constant so that it can be selected/changed even at runtime. Parameterized tiled loops facilitate iterative and runtime optimizations, such as iterative compilation, auto-tuning and dynamic program adaption. In this dissertation we present a collection of techniques for generating parameterized and multi-level tiled loops from affine control loops and their parallelization. The tiled loop generation problem even for perfectly nested loops has been believed to have an exponential time complexity due to the heavy machinery like Fourier-Motzkin elimination. Disproving this decade-long belief, we provide a simple technique for generating tiled loop nests even from imperfectly nested loops. Our technique for perfectly nested loops consists of only syntactic processing that is applied only once and independently to each loop bound. Our approach to imperfectly nested loops is composed of a direct extension of the tiled code generation technique for perfectly nested loops and three simple optimizations on the resulting parameterized tiled loops. The generation as well as the optimizations are achieved only with purely syntactic processing, hence loop generation time remains negligible. We also present three schemes for multi-level tiling where tiling is applied more than once. All the schemes are scalable with respect to the number of tiling levels and can be combined to achieve better performance. To facilitate parallelization of parameterized tiled loops, we generate outermost tile-loops that are perfectly nested. We also provide a technique for statically restructuring parameterized tiled loops to the wavefront scheduling on shared memory system. Because the formulation of parameterized tiling does not fit into the well established polyhedral framework, such static restructuring has been a great challenge. However, we achieve this limited restructuring through a syntactic processing without any sophisticated machinery. | |
| dc.format.medium | born digital | |
| dc.format.medium | doctoral dissertations | |
| dc.identifier | 2010_Summer_Kim_DaeGon.pdf | |
| dc.identifier | Kim_colostate_0053A_10039.pdf | |
| dc.identifier | ETDF2010100006COMS | |
| dc.identifier.uri | http://hdl.handle.net/10217/39103 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | tiling | |
| dc.subject | polyhedral model | |
| dc.subject | parallelization | |
| dc.subject | optimization | |
| dc.subject | compiler | |
| dc.subject | code generation | |
| dc.subject.lcsh | Loop tiling (Computer science) | |
| dc.subject.lcsh | Compilers (Computer programs) | |
| dc.subject.lcsh | Loops (Group theory) | |
| dc.subject.lcsh | Parallel processing (Electronic computers) | |
| dc.title | Parameterized and multi-level tiled loop generation | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Computer Science | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Doctoral | |
| thesis.degree.name | Doctor of Philosophy (Ph.D.) |
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