A systolic VLSI chip for implementing orthogonal transforms
Date
1989
Authors
Endsley, Neil H., author
Gabriel, Arthur R., author
Scharf, Louis L., author
Burleson, Wayne P., author
IEEE, publisher
Journal Title
Journal ISSN
Volume Title
Abstract
This paper describes the design of a systolic VLSI chip for the implementation of signal processing algorithms that may be decomposed into a product of simple real rotations. These include orthogonal transformations. Applications of this chip include projections, discrete Fourier and cosine transforms, and geometrical transformations. Large transforms may be computed by "tiling" together many chips for increased throughput. A CMOS VLSI chip containing 138 000 transistors in a 5x3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of fully synchronous bit-serial interconnect and a very regular structure at the rotator and bit levels. A distributed arithmetic scheme is used to implement the matrix-vector multiplication of the rotation.
Description
Rights Access
Subject
CMOS integrated circuits
VLSI
cellular arrays
computerised signal processing
digital arithmetic
digital signal processing chips
parallel architectures
pipeline processing
real-time systems
transforms